library verilog;
use verilog.vl_types.all;
entity cmsdk_apb_uart is
    port(
        PCLK            : in     vl_logic;
        PCLKG           : in     vl_logic;
        PRESETn         : in     vl_logic;
        PSEL            : in     vl_logic;
        PADDR           : in     vl_logic_vector(11 downto 2);
        PENABLE         : in     vl_logic;
        PWRITE          : in     vl_logic;
        PWDATA          : in     vl_logic_vector(31 downto 0);
        ECOREVNUM       : in     vl_logic_vector(3 downto 0);
        PRDATA          : out    vl_logic_vector(31 downto 0);
        PREADY          : out    vl_logic;
        PSLVERR         : out    vl_logic;
        RXD             : in     vl_logic;
        TXD             : out    vl_logic;
        TXEN            : out    vl_logic;
        BAUDTICK        : out    vl_logic;
        TXINT           : out    vl_logic;
        RXINT           : out    vl_logic;
        TXOVRINT        : out    vl_logic;
        RXOVRINT        : out    vl_logic;
        UARTINT         : out    vl_logic
    );
end cmsdk_apb_uart;
